Ancien Post-doctorant – ENS Lyon / LIP
→ du 01/06/2014 au 31/05/2016
Abstract: We combine the traditional checkpointing and rollback recovery strategies with verification mechanisms to address both fail-stop and silent errors.
The objective is to minimize either makespan or energy consumption. While DVFS is a popular approach for reducing the energy consumption, using lower speeds/voltages can increase the number of errors, thereby complicating the problem. We consider an application workflow whose dependence graph is a chain of tasks, and we study three execution scenarios: (i) a single speed is used during the whole execution; (ii) a second, possibly higher speed is used for any potential re execution; (iii) different pairs of speeds can be used throughout the execution. For each scenario, we determine the optimal checkpointing and verification locations (and the optimal speeds for the third scenario) to minimize either objective. The different execution scenarios are then assessed and compared through an extensive set of experiments.
Keywords : HPC, resilience, checkpoint, verification, failures, fail-stop error, silent data corruption